Magnetoresistive memory for a complex programmable logic device

ABSTRACT

The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function. The platforms include embedded programmable logic, and MRAM memory, the logic and MRAM memory communicatively coupled via an interconnect.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a divisional of U.S. patentapplication Ser. No. 10/061,660, filed Feb. 1, 2002, which is hereinincorporated by reference in its entirety.

FIELD OF THE INVENTION

[0002] The present invention generally relates to the field ofsemiconductors and semiconductor design, and particularly to anarchitecture for a configurable platform including magnetoresistivememory.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits have become a necessary part of everydaymodem society. From wireless phones and information handling systems, tohousehold appliances and data storage systems, a wide range ofintegrated circuits are utilized to provide a broad range offunctionality. To provide this functionality, integrated circuits mayneed to be specialized to have the functions necessary to achieve thedesired results, such as through the provision of an applicationspecific integrated circuit (ASIC). An ASIC is typically optimized for agiven function set, thereby enabling the circuit to perform thefunctions in an optimized manner. However, there may be a wide varietyof end-users desiring such targeted functionality, with each userdesiring different functionality for different uses.

[0004] Additionally, more and more functions are being included withineach integrated circuit. While providing a semiconductor device thatincludes a greater range of functions supported by the device, inclusionof this range further complicates the design and increases thecomplexity of the manufacturing process. Further, such targetedfunctionality may render the device suitable for a narrow range ofconsumers, thereby at least partially removing an “economy of scale”effect that may be realized by selling greater quantities of the device.

[0005] Thus, the application specific integrated circuit business isconfronted by the contradiction that the costs of design and manufacturedictate high volumes of complex designs. Because of this, the number ofcompanies fielding such custom designs is dwindling in the face of thoserapidly escalating costs.

[0006] Further, there are limited options, previously, for storing stateinformation on a platform device. In order to give the platform devicestate, a platform utilizes memory that may be written to and read fromto configure a platform or groups of platforms.

[0007] Therefore, it would be desirable to provide a platformarchitecture of the present invention.

SUMMARY OF THE INVENTION

[0008] Accordingly, the present invention is directed to anarchitecture. In a first aspect of the present invention, a system forproviding distributed functionality in an electronic environmentincludes a plurality of platforms suitable for providing a logicfunction. The platforms include embedded programmable logic and MRAMmemory, the logic and MRAM memory communicatively coupled via aninterconnect.

[0009] In a second aspect of the present invention, a data storagesystem includes an electronic data storage device suitable for thestorage of electronic data, an MRAM memory operable for the storage ofelectronic data utilizing a magnetoresistive effect and a controllercommunicatively coupled to the data storage device and the MRAM memory.The controller is suitable for controlling operations of the datastorage device, wherein the controller receives data for writing to theelectronic data storage device, the data is stored utilizing the MRAMmemory before writing to the electronic data storage

[0010] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory only and are not restrictive of the invention as claimed.The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate an embodiment of the invention andtogether with the general description, serve to explain the principlesof the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The numerous advantages of the present invention may be betterunderstood by those skilled in the art by reference to the accompanyingfigures in which:

[0012]FIG. 1 is an illustration of an embodiment of the presentinvention wherein a platform operable to embodiment embody the presentinvention is shown;

[0013]FIG. 2 is an illustration of an embodiment of the presentinvention wherein a plurality of platforms as shown in FIG. 1 areprovided in a fabric;

[0014]FIG. 3 is an illustration of an embodiment of the presentinvention wherein a plurality of platforms incorporating MRAM in a seaof platforms architecture is shown; and

[0015]FIG. 4 is an illustration of an electronic data storage systemincluding MRAM.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Reference will now be made in detail to the presently preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings.

[0017] Referring generally now to FIGS. 1 through 4, exemplaryembodiments of the present invention are shown. The present inventionprovides an architecture for an element for use as a design component inapplication specific integrated circuit (ASIC) or semiconductor design.Technical questions involving complex device design may be thought of intwo general areas, metamethodology and platform architecture.Metamethodology is a formal organizing architecture for defining andmanaging arbitrary semiconductor design flows in predictable, efficientways, which may be tailored to specific product and processcharacteristics. For instance, different flows may have differentcombinations of tools in them, and thus, the successful operations mayrequire the imposition of automated rule-based assessment of progressand error in order to allow designers to work productively at a higherlevel of abstraction than is available today.

[0018] As semiconductor designs progress along the deep sub-micronroadmap, and as the challenge of managing complexity becomes evergreater, the need to define building blocks of designs at higher levelsof abstraction becomes even more pressing. Such a higher-level buildingblock includes a “platform.”

[0019] Referring now to FIG. 1, an embodiment 100 of the presentinvention is shown wherein elements of an exemplary platform areprovided. A platform may include a combination of the followingelements: (1) embedded programmable logic 102, which in somecontemplated embodiments is analogous to field programmable gate array(FPGA) or complex programmable logic device (CPLD) cores that FPGAcompanies sell as complete devices; (2) reconfigurable cores 104 such asa findamental processor elements to which may be addedinstruction-specialized, application-specific instruction setextensions; (3) an advanced interconnect 106, which in contemplatedembodiments is scalable, and may be isochronous; (4) software models andheuristics 108; and (5) specialized memories 110, which may includenonvolatile structures like MRAM, which is a memory that is based on themagneto-resistive effect, as well as other memories as contemplated by aperson of ordinary skill in the art. Specialized one-time programmableflash memory may also be included.

[0020] Programmable logic 102 components may include blocks ofprogrammable gate arrays, “seas of adders”, CPLD structures, and othersuitable programmable circuit elements definable from a storedrepresentation, either at power-on, dynamically while in operation, andthe like.

[0021] Reconfigurable cores 104 may include a base processor design,plus instruction set extensions designed to carry out function-specificlogical and arithmetic operations with optimal efficiency. For instance,such reconfigurable cores may implement digital signal processinginstruction set enhancements.

[0022] An interconnect 106 architecture is provided to allow theprogrammable logic and the reconfigurable cores to communicate with oneanother and with associated memory blocks. Such an architecture maydefine a transport which is scalable in bandwidth and is inherentlyisochronous. Further, it may be realizable within a switching fabric,which permits complex, adaptive, interconnect and access paths to bedefined on the fly. Isochrony, through a universal time base, maysimplify the problems of closing timing in complex designs.

[0023] The software for the platform may include the developmentenvironment and its interface to the metamethodology, as well assoftware IP cores, which may be implemented on the platform components,and the customer-developed custom code implementing proprietary orfunctionally specific routines.

[0024] There are numerous ways of structuring logic blocks: such as thenumber of logic elements in an organization; the kinds of cores and thenumbers of cores; whether or not DSP-specific characteristics areincluded, and the like. Additionally, the characteristics of theinterconnect, software, and memory may all be varied in innumerabledifferent ways without departing from the spirit and scope of thepresent invention.

[0025] The present invention provides a platform, which may be embeddedin a methodological framework that allows designers to work with theplatform at a high level of abstraction. The complexity of theinteractions between elements may so great that by providingabstractions, the interactions may be rendered manageable and tractablefor designers that will use them practically.

[0026] Referring now to FIG. 2, an embodiment 200 of the presentinvention is shown wherein an architecture is configured as a sea ofplatforms. In this embodiment, a fabric is shown including a pluralityof platforms. Preferably, the platforms are connected utilizing similarprotocols, interconnect technology and interconnect architecture tounify the platforms in a single fabric.

[0027] Thus, a structure of the resources may be provided including thememory, reconfigurable cores, embedded programmable blocks, software andinterconnect, which communicates and intercommunicates coherently on anisochronous fabric. Such a structure may be suitable for providing a“programmable ASIC”. For instance, an application-neutral device may beconstructed with potential for accepting complex logic and definitionsthat are programmed completely independently of the fabrication of thedevice. This may be thought of as a decoupled model, in which thecontemplated implementation of the device as used by an end-user isdecoupled from the process of designing and manufacturing the physicaldevice itself.

[0028] Each of these intersections on this fabric, may contain one ormore processors, embedded programmable logic, memory, softwarecapabilities and its own interconnect internally, as described inrelation to FIG. 1. By providing this fabric including reconfigurablecores, the present invention may provide a targeted semiconductorproviding desired functionality without requiring specialized design andmanufacturing processes as previously required in ASIC manufacture.

[0029] For example, a manufacturer may receive a register transfer level(RTL) definition of a solution to a problem from a customer for aspecification. A customer may want to create, for instance, acommunications device, a storage device, a controller, a switchingproduct, a game controller for consumer application, a satellite TVset-up box, and the like, and supply an RTL specification for thedesired device to the manufacturer.

[0030] By utilizing the present invention, the RTL may be mapped intothe platform of the present invention to provide the desiredfunctionality as indicated by the RTL. For instance, instruction setarchitecture extensions may be utilized for mapping to thereconfigurable core the desired functionality. The extensions may becrafted to solve efficiently and specifically problems in encryption, inencoding or decoding, in modulation, in signal processing, in datatransformation of various kinds, and the like. Additionally, abstractlogic functions may be implemented, such as specialized shift registers,multiplexers (MUX), and the like as contemplated by a person of ordinaryskill in the art. Thus, an instruction set extension may be affiliatedwith a wide range of functionality.

[0031] An embedded programmable logic core (EPLC) block may be tied to aset of instruction set extensions such that the EPLC block would haveresponsibility under software control for invoking any of severalextensions to be active in a particular temporal episode. In this way,the “personality” of a reconfigurable core may be changed dynamicallyunder the control of this EPLC mechanism. Thus, in an aspect of thepresent invention, this may enable the mapping of an RTL efficientlyinto a sea of platforms. The constituents of one platform may allow anEPLC block to play a role when choosing appropriate instruction setextensions as needed, given the temporal evolution of the function thatthe block is fulfilling.

[0032] Isochronous Functionality

[0033] Referring again to FIG. 2, by providing an isochronous fabric,the register files of multiple processors in multiple platforms may beutilized as dynamically extensible. In other words, it is possiblebecause of the isochronous characteristic of the fabric, withoutadditional software or additional overhead, to synchronize andcoordinate the instruction-set extension operations on these registerfiles over as many platforms as needed, which may be thought of asextending horizontally across the fabric as desired to achieve thenecessary resources, such as processor power and the like, to fulfill aparticular complex logic function.

[0034] Arbitrary sets of logic functions may be deployed across registerfiles, and the instruction set extensions treated as general logicengines that are reconfigurable “on-the-fly,” on a cycle-by-cycle basis.For instance, given, (a), the provision of a proper instruction setextension or extensions to coordinate discrete, distinctive, differentinstruction set extensions on a cycle-by-cycle basis; and (b), that theexecution is synchronized, for instance, to ensure that the rightinstruction set extension is invoked in the right set of reconfigurablecores at the right cycle, the functions may be deployed acrossplatforms, operating as logic engines, as needed. Thus, by knowing thefunctionality of a register, where that functionality is located, andthe function of a register at a given point in time, logic functions maybe targeted to provide the functionality.

[0035] For example, in terms of actual behavior of applications in thereal world, loads vary, and functions vary as loads vary. By utilizingthe present invention, spatial distribution of functions across thearray may vary as a function of the dynamic changes in the functionalload that is actually being asked of a particular device.

[0036] To track these changes and provide the functionality, a map maybe maintained indicating the functionality of the platforms. Forinstance, in an aspect of the present invention, a master map ismaintained of the instantaneous distribution of functions across theplatforms. Such a map may be thought of as a functional virtualization,in which the map indicating corresponding functions and locations isfully virtualized. Thus, functional virtualization may be provided inaddition to a general logic capability previously discussed.

[0037] Because the isochronous foundation of this embodiment of thepresent invention, the isochronous fabric provides coordinatedsynchronization without the bookkeeping or overhead which may beassociated utilizing other methods. By providing a mapping of particularcomponents, i.e. what the particular components are set up to do whatparticular component of a function at what point in time, desiredfunctionality may be achieved in a coordinated fashion.

[0038] Compiler

[0039] In an additional aspect of the present invention, a smartcompiler is provided which “understands” how to manage and develop abinary executable for a particular instruction set extension. Further,the compiler technology may be generalized so that it has the propertyof extending this understanding, so that it may track which extensionsare mapped to which particular set of processors, and understandstemporally the load value, i.e. the cycle by cycle availability of aresource of a particular kind.

[0040] In effect, the compiler technology extends horizontally acrossprocessor function sets, so that the compiler, when an application,methodology and like program of instructions is expressed and translatedto the compiler, the compiler may determine availability of theresources. Additionally, through the use of an isochronous fabric, thereis no overhead associated with altering the connections. Reconfiguringthe functionality of a device employing the platforms may beaccomplished through changing the map.

[0041] The compiler technology of the present invention may implementthis space/time view through an arbitrarily extensible very largeinstruction word (VLIW) architecture that is variable. For example,although the architecture has been used in multimedia engines, the widthis cycle-by-cycle variable according to this aspect of the presentinvention.

[0042] The advantages of such a “smart” compiler are numerous. Forinstance, in cache management, a variety of considerations may beaccounted for, such as latency and the resultant performance penalty,associated overhead of flushing the cache versus maintaining a functionin place, and the like. Thus, a compiler of the present invention mayoptimize operations performed by the platforms.

[0043] Therefore, in an embodiment of the present invention, a compileris provided that is capable of maintaining space/time mapping of theinstruction set extensions over an isochronous fabric so thatcycle-by-cycle ability is maintained to affiliate objects andcommunicatively couple them as desired.

[0044] Mapping

[0045] To coordinate and provide desired functionality, a map of thepresent invention is provided. For instance, in an aspect of the presentinvention, RTL is expressed, in terms of combinations of instruction setarchitecture extensions and embedded programmable logic core (EPLC)blocks.

[0046] For example, in an aspect of the present invention, a map isprovided for describing functions of platforms of the present inventionexpressed in a graph-theoretic manner. A map may be provided as a graph,for instance, employing graph coloring and with efficientgraph-traversal algorithms to describe the interaction and functionalityof the components.

[0047] Formalisms may be employed for expressing functions, such asMUXs, latches, codecs, and like logic functions and re-expressing thefunctions in terms of efficient instruction set architecture (ISA)extensions. Preferably, the extensions take into account that somecomponents of the ISA may be modified on a cycle-by-cycle basis on theone hand and may be varied in width on the other hand.

[0048] For instance, standard library functions, such as concrete,practical, standard functions in an ASIC, may be expressed asmathematical abstracts. These mathematical abstracts may be expressed asinstruction set extensions and EPLC adjuncts that will allow theseinstructions to be manipulated rapidly. In one contemplated embodiment,ASIC library functions are implemented with minimal overhead penaltiesand space penalties.

[0049] In this way, the present invention provides two degrees offreedom in finding optimal expressions of logic functions that can bedeployed across the sea of platforms of the present invention.

[0050] Magnetoresistive Memory for a Complex Programmable Logic Device

[0051] The present invention may also include nonvolatile memoriesembedded in platforms. Traditionally, there were limited options forstoring state information on a platform device, such as a deviceincluding a microcontroller, a reconfigurable core, a DSP, embeddedprogrammable logic, and the like, which is communicatively coupled via ascalable interconnect. In order to give the platform device state, theplatform needs some kind of memory that may be written to and read fromto configure a chip. The state may be defined at manufacturing time, inthe field, such as sending the chip out into the field, and thenconfiguring the chip once it arrives, so that the state may becontextual, and the like as contemplated by a person of ordinary skillin the art.

[0052] In addition to defining state, it is also desirable that theplatform support repair functionality. For example, in an instance ofchip malfunction, a method of introducing a bug fix may be implemented,a self-healing mechanism employed that will allow the chip toreconfigure itself based on a previous definition, redefine theconfiguration of the chip based on changing needs, and the like. Forinstance, a new protocol standard may be encountered, and thus the chipmay need to be updated with the new standard in the field.

[0053] Traditionally, one way of providing this platform support hasbeen to include flash memories within a device. Flash memory is a formof writable nonvolatile memory that may be upgraded in the field.However, flash memory has several disadvantages. Flash memory isasymmetric and requires wear leveling.

[0054] For example, flash cells may wear from repeated writings.Therefore, although flash memory may be read repetitively with no harm,a memory location of flash memory may not be written a great multitudeof times. There is a wear phenomenon in which voltage required tosuccessfully write to a location gradually increases over time, and assoon as the voltage required to perform a write passes a certainthreshold, the device is no longer reliably writable at that location.Thus, the pattern of writes is distributed in a random fashion, i.e.wear leveling, to reduce hot spots that become unwritable. Flash memoryis also slow, expensive and is complicated to embed in an ASIC process,and thus, has severe limitations.

[0055] Thus, the provision of a reliable memory device may have asignificant impact on platform architecture. For example, by providing areliable memory, platform structures may have the ability to reliablyretain state even in the absence of power, which alters how designing aplatform and getting the platform to function is approached, because ofthe ability to have a complex instantaneously recorded state that ispreserved through random power interruptions.

[0056] By not having these advantages, a variety of considerations mustbe addressed. For instance, a platform may be provided that has asimpler functionality because the functionality has to be 100 percentdefined in the silicon, or the platform must have a secure way ofreturning to its desired configuration due to malfunction or otherfunctionality interruption, the platform has to be constructed as a“perfect” device because the platform does not have the ability to fixitself, and other considerations as contemplated by a person of ordinaryskill in the art. All of those constraints are lifted if a writablenonvolatile memory of the present invention is provided.

[0057] Additionally, it is expected that the proportion of a dieconsumed by memory will continue to increase. In other words, memory isgoing to occupy more and more of the die area and which is true whetherutilizing a sea of platforms architecture or the more traditionalprocessor and IP cores organization is utilized. This argues in favor ofthe emergence of a nonvolatile form that may retain its content eventhough the content may become quite large, such as multiple megabytes ofdata.

[0058] Therefore, the present invention provides MRAM for support of thedesired functionality. MRAM is a way of applying the magnetoresitiveeffect, including giant magnetoresistive effect and the like. MRAMincludes a set of characteristics that may have the effect of changinghow platform architectures are conceived and put together, because MRAMmay supply large, symmetrical, cheap, long-lasting nonvolatile memory.Symmetrical and asymmetrical may refer to reading and writing, as wellas access time and energy.

[0059] GMR technology, such as the technology used in heads of diskdrives, exploits a tunneling phenomenon in quantum electronics. Althoughthere is some debate about the theoretical underpinnings of GMR, from apragmatic point of view, it is a well understood issue.

[0060] The inclusion of MRAM in a platform of the present invention mayprovide a wide range of desired behaviors. For example, if a memoryblock included in a platform is all or largely MRAM, a variety ofbeneficial behaviors may be provided; very large memory areas may beprovided; a plurality of megabytes may be written arbitrarily; thememory is reliable; the content is symmetrical (in other words, theamount of energy required to write is essentially equivalent to theamount of energy required to read, which is not true with flash); andthe like. These behaviors allow definition of a state of high complexitythat may be completely independent in the device itself and may beinterrogated and updated remotely with little or no risk. Because flashis slow to write, requires wear leveling and has a finite lifetime,state information may not be updated in the device in the nonvolatilememory space utilizing flash memory a multitude of times, and thus,requires the additional considerations previously described to beaddressed.

[0061] The use of MRAM may have a profound impact on how platforms arestructured in the future. The MRAM approach provides the capability ofaccommodating a vastly greater range of states in a platform device'sstate space which may be reliably and dependably updated andinterrogated. Secure encryption may also be utilized so the content maybe nonvolatile but still secure and interrogatable only from a remotetrusted authority.

[0062] This functionality changes platform character because now thecontrol codes that define the state of the platform, (such as a sea ofplatforms, which may be an immensely complex system environment) may bewritten into a symmetrical low-cost, high-density writable nonvolatilememory that may be upgraded and interrogated at will. The state memorymay be updated rapidly and securely in order to make sure that thedevice stays on-line.

[0063] For example, referring now to the embodiment shown in FIG. 3, asea of platforms architecture may be provided in which each of theplatforms has a corresponding MRAM for storage of state information. Byincluding state information within the platforms themselves, the stateinformation may be accessible even in the case of power failure, and maybe written and accessed a multitude of times without the problems ofwear-leveling as required in utilizing flash memory. Although MRAM isshown within each platform, MRAM may be distributed through the “sea ofplatforms” utilizing a variety of methods without departing from thespirit and scope thereof, such as in platform groupings and the like.

[0064] The use of MRAM may also result in increased yields due to therepair capability. For instance, repair capabilities may include complexrepair algorithms, redundant resources on the device that may be invokedremotely when malfunction of the device is detected, and the like. Thus,the ability to repair a platform including this architecture maydecrease production costs, improve device operability and increaseperformance of the platform incorporating this functionality.

[0065] Genetic programming may also be greatly improved, such as ininstances in which a chip computes among a multitude of possibilities,MRAM provides the memory characteristics needed to facilitate thisaccess. For instance, where the patterns of access are heavilyconcentrated in a very small number of locations for intense periods oftime, flash is ill-suited for computationally intensive environmentswhere writes need to be performed into the nonvolatile space.Additionally, many algorithms either require such access or are heavilyoptimized on the assumption of the ability to write into a nonvolatilespace repetitively and intensively.

[0066] Further, this nonvolatile, as opposed to volatile, memory mayhave improved power consumption, power management functionality, as wellas support disaster recovery as described previously.

[0067] In another embodiment of the present invention shown in FIG. 4,MRAM is incorporated into a data storage system. For instance, thecontrol of large repositories, such as a RAID array including multipledata storage devices 402, 404 & 406, disk farms and the like, may beprovided in which a write operation needs to be performed for storage ofdata. However, the disk may have high latency, delayed operation in theinstance of a swappable disk, and the like.

[0068] To provide reliable data storage, an area of nonvolatile memory,in this case MRAM 410, is provided so that in the case of power failure,device malfunction, and the like, that state information is capturedeven before it has been committed to the very high-latency medium thatis represented by a disk drive and the like. For example, the MRAMrepository 410 may be accessible by a controller 408 of a RAID array, inwhich data is first received by the controller and written to the MRAM410 before being transferred to the data storage devices 402, 404 & 406.Thus, the design of controllers 408 for large repositories will beheavily affected by the availability of these symmetrical nonvolatilememories.

[0069] It is believed that the architecture of the present invention andmany of its attendant advantages will be understood by the foregoingdescription. It is also believed that it will be apparent that variouschanges may be made in the form, construction and arrangement of thecomponents thereof without departing from the scope and spirit of theinvention or without sacrificing all of its material advantages. Theform herein before described being merely an explanatory embodimentthereof. It is the intention of the following claims to encompass andinclude such changes.

What is claimed is:
 1. A system for providing distributed dynamicfunctionality in an electronic environment comprising: a plurality ofplatforms, the platforms suitable for providing a logic function, theplatforms including embedded programmable logic and MRAM memory, thelogic and MRAM memory communicatively coupled via an interconnect. 2.The system as described in claim 1, further comprising a reconfigurablecore.
 3. The system as described in claim 1, further comprising a mapexpressing logic function of the plurality of platforms.
 4. A datastorage system, comprising: an electronic data storage device suitablefor the storage of electronic data; an MRAM memory, the MRAM memoryoperable for the storage of electronic data utilizing a magnetoresistiveeffect; and a controller communicatively coupled to the data storagedevice and the MRAM memory; the controller suitable for controllingoperations of the data storage device, wherein the controller receivesdata for writing to the electronic data storage device; the data isstored utilizing the MRAM memory before writing to the electronic datastorage device.
 5. The data storage system as described in claim 4,wherein the electronic data storage device is a disk drive.
 6. The datastorage system as described in claim 4, further comprising a secondelectronic data storage device, the electronic data storage device andthe second electronic data storage device arranged with the controlleras a RAID system.
 7. The data storage system as described in claim 4,wherein the MRAM memory is utilized as a buffer by the controller. 8.The data storage system as described in claim 4, wherein the MRAM memoryis symmetrical.
 9. The data storage system as described in claim 8,wherein an amount of energy required to write to the MRAM memory isgenerally equivalent to an amount of energy required to read the MRAMmemory.
 10. A data storage system, comprising: a means for storingelectronic data; a means for storing electronic data utilizing amagnetoresistive effect; and a means for controlling operations of thedata storage means, the controlling means communicatively coupled to thedata storage means and the magnetoresistive data storage means; whereinthe controlling receives data for writing to the data storage means, thedata is stored utilizing the magnetoresistive data storage means beforewriting to the data storage means.
 11. The data storage system asdescribed in claim 10, wherein the data storage means is a disk drive.12. The data storage system as described in claim 10, further comprisinga second means for storing electronic data, the data storage means andthe second data storage means arranged with the controlling means as aRAID system.
 13. The data storage system as described in claim 10,wherein the magnetoresistive data storage means is utilized as a bufferby the controller.
 14. The data storage system as described in claim 10,wherein the magnetoresistive data storage means is symmetrical.